BeagleBone Black Pins

Evan Boldt's picture

Pinout Tables

These tables are based on the BeagleBone Black System Reference Manual (Creative Commons) by Gerald Coley of BeagleBoard.org. They aren't really available anywhere else on the internet, so I thought I'd transcribe them into a more available format.

The PROC column is the pin number on the processor.

The PIN column is the pin number on the expansion header.

The MODE columns are the mode setting for each pin. Setting each mode to align with the mode column will give that function on that pin. Each pin's mode can be set individually.

Note that the MODE5 column is absent. That is not a typo. It just doesn't do anything. The only exception is GPIO0_7 in expansion header P9 has a mmc0_sdwp

Expansion Header P8 Pinout
PINPROCNAMEMODE0MODE1MODE2MODE3MODE4MODE6MODE7
1,2 GND
3 R9 GPIO1_6 gpmc_ad6 mmc1_dat6         gpio1[6]
4 T9 GPIO1_7 gpmc_ad7 mmc1_dat7         gpio1[7]
5 R8 GPIO1_2 gpmc_ad2 mmc1_dat2         gpio1[2]
6 T8 GPIO1_3 gpmc_ad3 mmc1_dat3         gpio1[3]
7 R7 TIMER4 gpmc_advn_ale   timer4       gpio2[2]
8 T7 TIMER7 gpmc_oen_ren   timer7       gpio2[3]
9 T6 TIMER5 gpmc_be0n_cle   timer5       gpio2[5]
10 U6 TIMER6 gpmc_wen   timer6       gpio2[4]
11* R12 GPIO1_13 gpmc_ad13 lcd_data18 mmc1_dat5* mmc2_dat1 eQEP2B_in   gpio1[13]
12* T12 GPIO1_12 gpmc_ad12 lcd_data19 mmc1_dat4* mmc2_dat0 EQEP2A_IN   gpio1[12]
13* T10 EHRPWM2B gpmc_ad9 lcd_data22 mmc1_dat1* mmc2_dat5 ehrpwm2B   gpio0[23]
14* T11 GPIO0_26 gpmc_ad10 lcd_data21 mmc1_dat2* mmc2_dat6 ehrpwm2_tripzone   gpio0[26]
15* U13 GPIO1_15 gpmc_ad15 lcd_data16 mmc1_dat7* mmc2_dat3 eQEP2_strobe   gpio1[15]
16* V13 GPIO1_14 gpmc_ad14 lcd_data17 mmc1_dat6* mmc2_dat2 eQEP2_index   gpio1[14]
17* U12 GPIO0_27 gpmc_ad11 lcd_data20 mmc1_dat3* mmc2_dat7 ehrpwm0_synco   gpio0[27]
18 V12 GPIO2_1 gpmc_clk_mux0 lcd_memory_clk gpmc_wait1 mmc2_clk   mcasp0_fsr gpio2[1]
19* U10 EHRPWM2A gpmc_ad8 lcd_data23 mmc1_dat0* mmc2_dat4 ehrpwm2A   gpio0[22]
20* V9 GPIO1_31 gpmc_csn2 gpmc_be1n mmc1_cmd*       gpio1[31]
21* U9 GPIO1_30 gpmc_csn1 gpmc_clk mmc1_clk*       gpio1[30]
22 V8 GPIO1_5 gpmc_ad5 mmc1_dat5         gpio1[5]
23 U8 GPIO1_4 gpmc_ad4 mmc1_dat4         gpio1[4]
24 V7 GPIO1_1 gpmc_ad1 mmc1_dat1         gpio1[1]
25 U7 GPIO1_0 gpmc_ad0 mmc1_dat0         gpio1[0]
26 V6 GPIO1_29 gpmc_csn0           gpio1[29]
27* U5 GPIO2_22 lcd_vsync* gpmc_a8         gpio2[22]
28* V5 GPIO2_24 lcd_pclk* gpmc_a10         gpio2[24]
29* R5 GPIO2_23 lcd_hsync* gpmc_a9         gpio2[23]
30* R6 GPIO2_25 lcd_ac_bias_en* gpmc_a11         gpio2[25]
31* V4 UART5_CTSN lcd_data14* gpmc_a18 eQEP1_index mcasp0_axr1 uart5_rxd uart5_ctsn gpio0[10]
32* T5 UART5_RTSN lcd_data15* gpmc_a19 eQEP1_strobe mcasp0_ahclkx mcasp0_axr3 uart5_rtsn gpio0[11]
33* V3 UART4_RTSN lcd_data13* gpmc_a17 eQEP1B_in mcasp0_fsr mcasp0_axr3 uart4_rtsn gpio0[9]
34* U4 UART3_RTSN lcd_data11* gpmc_a15 ehrpwm1B mcasp0_ahclkr mcasp0_axr2 uart3_rtsn gpio2[17]
35* V2 UART4_CTSN lcd_data12* gpmc_a16 eQEP1A_in mcasp0_aclkr mcasp0_axr2 uart4_ctsn gpio0[8]
36* U3 UART3_CTSN lcd_data10* gpmc_a14 ehrpwm1A mcasp0_axr0   uart3_ctsn gpio2[16]
37* U1 UART5_TXD lcd_data8* gpmc_a12 ehrpwm1_tripzone mcasp0_aclkx uart5_txd uart2_ctsn gpio2[14]
38* U2 UART5_RXD lcd_data9* gpmc_a13 ehrpwm0_synco mcasp0_fsx uart5_rxd uart2_rtsn gpio2[15]
39* T3 GPIO2_12 lcd_data6* gpmc_a6   eQEP2_index     gpio2[12]
40* T4 GPIO2_13 lcd_data7* gpmc_a7   eQEP2_strobe pr1_edio_data_out7   gpio2[13]
41* T1 GPIO2_10 lcd_data4* gpmc_a4   eQEP2A_in     gpio2[10]
42* T2 GPIO2_11 lcd_data5* gpmc_a5   eQEP2B_in     gpio2[11]
43* R3 GPIO2_8 lcd_data2* gpmc_a2   ehrpwm2_tripzone     gpio2[8]
44* R4 GPIO2_9 lcd_data3* gpmc_a3   ehrpwm0_synco     gpio2[9]
45* R1 GPIO2_6 lcd_data0* gpmc_a0   ehrpwm2A     gpio2[6]
46* R2 GPIO2_7 lcd_data1* gpmc_a1   ehrpwm2B     gpio2[7]

 * some pins are used by the internal storage (eMMC), and HDMI. 11-21 are used by eMMC.  27-46 are used by HDMI. 

Expansion Header P9 Pinout
PINPROCNAMEMODE0MODE2MODE3MODE4MODE6MODE7
1,2 GND
3,4 DC_3.3V
5,6 VDD_5V
7,8 SYS_5V
9 PWR_BUT
10 A10 RESET_OUT            
11 T17 gpmc_wait0 mii2_crs gpmc_csn4 rmii2_crs_dv mmc1_sdcd uart4_rxd_mux2 gpio0[30]
12 U18 gpmc_be1n mii2_col gpmc_csn6 mmc2_dat3 gpmc_dir mcasp0_aclkr_mux3 gpio1[28]
13 U17 gpmc_wpn mii2_rxerr gpmc_csn5 rmii2_rxerr mmc2_sdcd uart4_txd_mux2 gpio0[31]
14 U14 gpmc_a2 mii2_txd3 rgmii2_td3 mmc2_dat1 gpmc_a18 ehrpwm1A_mux1 gpio1[18]
15 R13 gpmc_a0 gmii2_txen rmii2_tctl mii2_txen gpmc_a16 ehrpwm1_tripzone gpio1[16]
16 T14 gpmc_a3 mii2_txd2 rgmii2_td2 mmc2_dat2 gpmc_a19 ehrpwm1B_mux1 gpio1[19]
17 A16 spi0_cs0 mmc2_sdwp I2C1_SCL ehrpwm0_synci     gpio0[5]
18 B16 spi0_d1 mmc1_sdwp I2C1_SDA ehrpwm0_tripzone     gpio0[4]
19 D17 uart1_rtsn timer5 dcan0_rx I2C2_SCL spi1_cs1   gpio0[13]
20 D18 uart1_ctsn timer6 dcan0_tx I2C2_SDA spi1_cs0   gpio0[12]
21 B17 spi0_d0 uart2_txd I2C2_SCL ehrpwm0B   EMU3_mux1 gpio0[3]
22 A17 spi0_sclk uart2_rxd I2C2_SDA ehrpwm0A   EMU2_mux1 gpio0[2]
23 V14 gpmc_a1 gmii2_rxdv rgmii2_rxdv mmc2_dat0 gpmc_a17 ehrpwm0_synco gpio1[17]
24 D15 uart1_txd mmc2_sdwp dcan1_rx I2C1_SCL     gpio0[15]
25 A14 mcasp0_ahclkx eQEP0_strobe mcasp0_axr3 mcasp1_axr1 EMU4_mux2   gpio3[21]
26 D16 uart1_rxd mmc1_sdwp dcan1_tx I2C1_SDA     gpio0[14]
27 C13 mcasp0_fsr eQEP0B_in mcasp0_axr3 mcasp1_fsx EMU2_mux2   gpio3[19]
28 C12 mcasp0_ahclkr ehrpwm0_synci mcasp0_axr2 spi1_cs0 eCAP2_in_PWM2_out   gpio3[17]
29 B13 mcasp0_fsx ehrpwm0B   spi1_d0 mmc1_sdcd_mux1   gpio3[15]
30 D12 mcasp0_axr0 ehrpwm0_tripzone   spi1_d1 mmc2_sdcd_mux1   gpio3[16]
31 A13 mcasp0_aclkx ehrpwm0A   spi1_sclk mmc0_sdcd_mux1   gpio3[14]
32   VADC
33 C8 AIN4
34   AGND
35 A8 AIN6
36 B8 AIN5
37 B7 AIN2
38 A7 AIN3
39 B6 AIN0
40 C7 AIN1
41# D14 xdma_event_intr1   tclkin clkout2 timer7_mux1 EMU3_mux0 gpio0[20]
D13 mcasp0_axr1 eQEP0_index   Mcasp1_axr0 emu3   gpio3[20]
42@ C18 eCAP0_in_PWM0_out uart3_txd spi1_cs1 pr1_ecap0_ecap
_capin_apwm_o
spi1_sclk xdma_event_intr2 gpio0[7]
B12 Mcasp0_aclkr eQEP0A_in Mcaspo_axr2 Mcasp1_aclkx     gpio3[18]

Selecting Modes

Using the "everything is a file" sys directory, you can use BASH or whatever to change the mode number for the pin in the NAME column.

echo 7 > /sys/kernel/debug/omap_mux/gpmc_ad4
echo 36 > /sys/class/gpio/export
echo out > /sys/class/gpio/gpio32/direction
echo 1 > /sys/class/gpio/gpio32/value

If you are using windows, TI has this GUI you can use called PinMuxTool / Pin Mux Utility. The BBB is AM335x r2 based.

The above only works if you're using the older kernel. The new 3.8 based kernel is missing this nifty pin mux feature. However, you can still check what they're muxed at even if you can't change them easily at runtime by looking at

/sys/kernel/debug/pinctrl/44e10800.pinmux/pingroups
root@arm:/sys/kernel/debug/pinctrl/44e10800.pinmux# cat pingroups 
registered pin groups:
group: pinmux_userled_pins
pin 21 (44e10854)
pin 22 (44e10858)
pin 23 (44e1085c)
pin 24 (44e10860)

group: pinmux_rstctl_pins
pin 20 (44e10850)

group: pinmux_i2c0_pins
pin 98 (44e10988)
pin 99 (44e1098c)

group: pinmux_i2c2_pins
pin 94 (44e10978)
pin 95 (44e1097c)

group: pinmux_emmc2_pins
pin 32 (44e10880)
pin 33 (44e10884)
pin 0 (44e10800)
pin 1 (44e10804)
pin 2 (44e10808)
pin 3 (44e1080c)
pin 4 (44e10810)
pin 5 (44e10814)
pin 6 (44e10818)
pin 7 (44e1081c)

group: pinmux_userled_pins
pin 21 (44e10854)
pin 22 (44e10858)
pin 23 (44e1085c)
pin 24 (44e10860)

group: mcasp0_pins
pin 107 (44e109ac)
pin 103 (44e1099c)
pin 101 (44e10994)
pin 100 (44e10990)
pin 106 (44e109a8)

group: nxp_hdmi_bonelt_pins
pin 108 (44e109b0)
pin 40 (44e108a0)
pin 41 (44e108a4)
pin 42 (44e108a8)
pin 43 (44e108ac)
pin 44 (44e108b0)
pin 45 (44e108b4)
pin 46 (44e108b8)
pin 47 (44e108bc)
pin 48 (44e108c0)
pin 49 (44e108c4)
pin 50 (44e108c8)
pin 51 (44e108cc)
pin 52 (44e108d0)
pin 53 (44e108d4)
pin 54 (44e108d8)
pin 55 (44e108dc)
pin 56 (44e108e0)
pin 57 (44e108e4)
pin 58 (44e108e8)
pin 59 (44e108ec)

group: nxp_hdmi_bonelt_off_pins
pin 108 (44e109b0)

Check Pin Statuses

root@beaglebone:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, gpio:

GPIOs 32-63, gpio:
 gpio-52  (eMMC_RSTn           ) out lo
 gpio-53  (beaglebone:green:usr) out lo
 gpio-54  (beaglebone:green:usr) out lo
 gpio-55  (beaglebone:green:usr) out hi
 gpio-56  (beaglebone:green:usr) out lo
 gpio-59  (McASP Clock Enable P) out hi

GPIOs 64-95, gpio:

GPIOs 96-127, gpio:

Power Limitations

Be careful about this one, there are some much lower limits than you might be used to

Pin Type Maximum Voltage Maximum Current
AIN 1.8V  
GPIO 3.3V 4mA - 6mA
VDD 3.3 3.3V 250mA
VDD 5V 5V* 1000mA *
SYS 5V 5V 250mA
VDD ADC 1.8V 0?
SYS 5V 5V 250mA

* VDD only works when the 5V barrel jack is used

i2c

It is recommended that you use I2C2 on pins 19 and 20 with the /dev/i2c-3 device.

Mode Name Port Physical Pin Number Block Device
I2C1 P9 17 & 18 or 24 & 26 ?
I2C2 P9 19 & 20 or 21 & 22 /dev/i2c-3

To check which i2c interfaces are avaible, check

root@arm:~# ls -l /dev/i2c*
crw-rw---- 1 root i2c 89, 0 Jun 5 04:34 /dev/i2c-0 crw-rw---- 1 root i2c 89, 1 Jun 5 04:34 /dev/i2c-1

To see what addresses are being used, try the i2cdetect command. In the below example, I have a temperature sensor hooked up to pins 19 and 20 that is using 48. Also note that the UU addresses are being used by the system and are unavailable.

root@beaglebone:~# i2cdetect -y -r 3
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- -- 
10: -- -- -- -- -- -- -- -- -- -- -- UU -- -- -- -- 
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
40: -- -- -- -- -- -- -- -- 48 -- -- -- -- -- -- -- 
50: -- -- -- -- UU UU UU UU -- -- -- -- -- -- -- -- 
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
70: -- -- -- -- -- -- -- --
Topics: 
Attachments: